The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors and the like.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that controls the current in the channel between the source and drain regions.
For proper operation of the MOS device, current should not flow between the source and drain regions of one MOS-type transistor to that of another transistor. During the manufacturing process, however, movement of dopant atoms, such as boron, can occur in the form of diffusion within the solid silicon of the wafer. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and dopant atoms diffusing into the silicon wafer and is typical in connection with forming p-type and n-type regions of a silicon integrated circuit device. Therefore, one important step in the manufacture of such devices is the formation of isolation areas to electrically separate the MOS devices.
Local oxidation of silicon (LOCOS) and shallow trench isolation (STI) are techniques that have been used in the past to limit diffusion in the silicon and to limit leakage current. STI has the advantage of allowing for higher device density by decreasing the required width of the semiconductor device isolating structure and can enhance surface planarity, thereby considerably improving critical dimension control during the lithographic process. One of the disadvantages to STI is the formation of sharp corners at the interface of the vertically oriented sidewalls and the top surface of the substrate. In efforts to round these sharp corners, the STI process has been further complicated, resulting in increased cost, decreased throughput and reduced yields.
Many processes used in the fabrication of integrated circuits generate stress in the silicon substrate. Given enough stress, the substrate will yield by forming dislocations that can glide into device regions. Shallow trench isolation processes are known to generate high stress in the silicon substrate. In the STI process, the subsequent oxidation (which generates self-interstitials) and implantation (which generates point defects) can contribute to nucleation of dislocations. Several methods have been developed to minimize the dislocations, including changes to the layout of the device, significant changes to the etch process, changes to the ion implantation process and changes to the annealing of the ion implant damage. High temperature corner oxidation cycles prior to the removal of an overlying nitride layer have typically been used to prevent dislocations, but this approach has not been totally satisfactory and is complicated to implement.
Accordingly, a need exists for developing a method for manufacturing semiconductor devices on semiconductor substrates that addresses the above-mentioned concerns and reduces stress-induced dislocations in the silicon substrate while increasing production yields.